The semiconductor device industry has a market-driven need to reduce the size of devices used, for example, in dynamic random access memories (DRAMs) that are found in computers and mobile communications systems. Currently, the industry relies on the ability to reduce or scale the dimensions of its basic devices to increase device density. This includes scaling the channel length of the metal oxide semiconductor field effect transistor (MOSFET). Increased channel scaling of the MOSFET can lower the channel resistance. Consequently, channel leakage currents may increase. This relationship has made the present MOSFET channel design less useful for providing increasingly smaller memory cells, and thus, there is a need to find other mechanisms to generate reduced cell geometry.